History Of Computer Architecture First Generation Information Technology Essay

History Of Computer Architecture First Generation Information Technology Essay In 1945 Electronic Numerical Integrator And Computer it was the first general purpose computer designed by Mauchly Echert, built by United States army to calculate  artillery  firing tables for ballistic shells during World War II. The machine was developed using vacuum tubes and relays, and it was programmed to work manually by setting switches. UNIVersal  Automatic  Computer  I (UNIVAC) 1950: It was the first commercial computer developed. John Von Neumann architecture: Goldstine and Von Neumann took the idea of ENIAC and developed concept of storing a program in the memory. Known as the Von Neumann architecture and has been the basis for virtually every machine designed since then. Features: Electron emit devices Data and programs are stored in a single read-write memory Memory contents are addressable by location, regardless of the content itself Machine language/Assemble language Sequential execution Second Generation (1950-1964) Transistors William Shockley, John Bardeen, and Walter Brattain invent the transistor that reduce size of computers and improve reliability. First operating Systems: handled one program at a time On-off switches controlled by electricity High level languages Floating point arithmetic Third Generation (1964-1974) Integrated Circuits (IC) Microprocessor chips combines thousands of transistors, entire circuit on one computer ship Semiconductor memory Multiple computer models with different performance characteristics Smaller computers that did not need a specialized room Fourth Generation (1974-present) Very Large-Scale Integration (VLSI)/Ultra Large Scale Integration (ULSI) Combines millions of transistors Single-chip processor and the single-board computer emerged Creation of the Personal Computer (PC) Wide spread use of data communications Artificial intelligence: Functions logic predicates Object-Oriented programming: Objects operations on objects Massively parallel machine 32 bit architecture In computing 32 bit architecture refers to how a computer is build. In a 32 bit architecture computer the integer values can be stored in 32bits is 0 through 4,294,967,295 or à ¢Ã‹â€ Ã¢â‚¬â„¢2,147,483,648 through 2,147,483,647 using twos complement encoding. Bus architecture In  computer architecture a  bus  refers to structure handling data transmission between components inside a  computer system, or computer network which transmit binary numbers, one bit per wire. Modern computer buses can use both parallel and bit-serial connections, and can be wired in either a electrical parallel or  daisy chain  topology, or connected by switched hubs, as in the case of  USB. A microprocessor communicates with memory and other devices (input and output) using three busses: Address Bus Data Bus Control Bus. Address Bus   The address bus  is a  computer bus, which consist series of lines connecting two or more devices that is used to specify a  physical address. When R3900  processor   needs to read or write to a memory location, it specifies that memory location on the address bus sent through the  data bus. The width of the address bus determines the amount of memory a system can address. In toshiba R3900 Processor Core address bus can address 232  (4,294,967,296) memory locations which is 32bit. If each memory address holds one byte, the addressable memory space is 4 GB. Address bus is unidirectional, numbers only sent from microprocessor to memory, not other way. Data Bus A data bus is a  computer  subsystem that allows for the transferring of data from one component to another on a  motherboard  or system board. Data bus used to transmit data, information, results of arithmetic, etc, between memory and the microprocessor This can include transferring data to and from the memory, or from the  central processing unit  (CPU) to other components, it is bi-directional. The R3900 data bus is designed to handle so many bits of data at a time. The amount of data a data bus can handle is called bandwidth. The toshiba 32 bits R3900  processor  can transfer data through a data bus every second. At the same time they are making data buses to handle more bits, they are also making devices that can handle those higher bitrates Control Bus A  control bus  is (part of) a  computer bus, used by  CPUs  for communicating with other devices within the computer. The control bus will tell the memory that we are either reading from a location, specified on the address bus, or writing to a location specified. Various other signals to control and coordinate the operation of the system. The R3900 32 bit buss, which allow larger number of instructions, more memory location, and faster arithmetic. Microcontrollers organized along same lines, except: because microcontrollers have memory etc inside the chip, the busses may all be internal. In the microprocessor the three busses are external to the chip (except for the internal data bus). In external busses, the chip connects to the busses via buffers, which are simply an electronic connection between external bus and the internal data bus. Memory management unit  (MMU) Memory management unit  (MMU) is also called as  paged memory management unit  (PMMU), is a  computer hardware component responsible for handling accesses to  memory  requested by the  CPU. Its functions include translation of  virtual addresses  to  physical addresses  (i.e.,  virtual memory  management),  memory protection,  cache  control,  bus  arbitration, and, in simpler computer architectures, bank switching. The functions performed by the memory management unit can typically be divided into three areas: hardware memory management operating system  memory management application memory management The Toshiba R3900 Processor Core Operating Modes The R3900 Processor Core has two operating modes user mode kernel mode It operates in the user mode normally, when exception is detected it changes to kernel mode. In kernel mode, it continues until an RFE (Restore from Exception) instruction is executed. The existing virtual address space varies with the mode. User mode User mode exist only one of the two 2 Gbyte virtual address spaces (kuseg). The most considerable bit of each kuseg address is 0. The range virtual address kuseg is of 0x0000 0000 to 0x7FFF FFFF. Attempting to access an address when the MSB is 1 while in user mode returns an Address Error exception. Kernel mode Kernel mode makes available a second 2 Gbyte virtual address space (kseg), in addition to the kuseg accessible in user mode. The range virtual address kuseg is of 0x8000 0000 to 0xFFFF FFFF. Direct Segment Mapping The Toshiba R3900 Processor Core has a direct segment mapping MMU. User mode One 2 Gbyte virtual address space (kuseg) is available in user mode. In this mode, the most important bit of each kuseg address is 0. The virtual address range of kuseg is 0x0000 0000 to 0x7FFF FFFF. Attempting to access an address outside of this range, that is, with the MSB is 1, while in user mode will raise an Address Error exception. Virtual addresses 0x0000 0000 to 0x7FFF. FFFF are translated to physical addresses 0x4000 0000 to 0xBFFF FFFF, individually. The upper 16-Mbyte area of kuseg (0x7F00 0000 to 0x7FFF FFFF) is reserved for on-chip resources and is not cacheable. Kernel mode The kernel mode address space is ta as four virtual address segments. One of these, kuseg, is the same as the one in user mode; the other remaining three are kernel segments kseg0, kseg1 and kseg2. Pipeline Architecture Computer  pipeline  is a set of data processing parts connected in series, so that the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion; in that case, some amount of  buffer storage  is often inserted between elements. Each cycle different instruction is executed in different stages For example, 5-stage pipeline (Fetch-Decode-Read-Execute-Write), The Toshiba R3900 Processor Core executes instructions in five pipeline stages (F: instruction fetch; D: decode; E: execute; M: memory access; W: register write-back). The five stages have the following roles. F : An instruction is fetched from the instruction cache. D : The instruction is decoded. Contents of the general-purpose registers are read.. E : Arithmetic, logical and shift operations are performed. The execution of multiple/divide instructions is begun. M: The data cache is accessed in the case of load and store instructions. W: The result is written to a general register. Each of the above pipeline stage is executed in one clock cycle. When the pipeline is fully used, the five instructions are executed at the same time, which will be resulting in an average instruction execution rate of one instruction per cycle. Delay Slot The R3900 Processor Core instructions are executed with a delay of one instruction cycle. Delay slot is the cycle in which an instruction is delayed. A delay occurs with load instructions and branch/jump instructions. Delayed load Delayed branching Non blocking Load Function In the R3900 processor the non blocking load function stops the pipeline from stalling when a cache miss happens and a refill cycle is needed to refill the data cache. Instructions after the load instruction that do not use registers involved by the load will continue to be executed. Multiply and Multiply/Add Instructions(MULT, MULTU, MADD, MADDU) The R3900 Processor Core is able to execute multiply and multiply/add instructions continuously, and able to use the results in the HI/LO registers in immediately following instructions, without pipeline stall. The processor requires only one clock cycle to use the outcome of a general-purpose register. Divide Instruction (DIV, DIVU) The Processor Core performs division instructions in the division unit independently of the pipeline. Division starts from the pipeline E stage and takes 35 cycles. Streaming The R3900 Processor Core can resume execution immediately after arrival of necessary data or instruction in cache even though cache refill operation is not completed during a cache refill operation. This is referred to as streaming.